1. Field of the Invention
The present invention relates to radio receivers which utilize a battery saving technique in which electrical power to the receiver is periodically switched off and on. More particularly, the invention relates to a data limiter that is directly coupled to the output of a receiver, the limiter having maximum and minimum signal level detectors to detect the corresponding values of the received and amplified waveforms and to average these values to automatically and rapidly adjust the bias on the limiter to compensate for changes in the bias voltage level of the receiver output waveform.
2. Background of the Invention
Radio receivers consist of a radio frequency apparatus that both receives and demodulates signals that are transmitted or conveyed over some communications channel. A more specialized form of receiver is a selective calling receiver which also includes a selective signaling decoder that is coupled to the output of the receiver and responds to the reception of predetermined signals. In the case of radio paging devices, for example, the communication channel is a radio frequency link, the communication receiver is a radio receiver and frequently an FM receiver, which demodulates the information that has been impressed on the radio frequency signal, and the decoder responds to predetermined calling signals which may be contained in the demodulated information. The predetermined calling signals identify and actuate an alert in an individual receiver that has been selectively called among a large population of receivers operating on the same radio frequency link.
Paging receivers are generally battery powered and utilize power saving techniques in which the receiver portion and in some cases parts of the decoder are periodically switched OFF and ON in a cyclical manner to conserve power and prolong battery life. A typical battery saver cycle time scheme may switch the receiver ON for approximately 100 miliseconds during every one second interval. During the ON time, the receiver and a signal detection circuit in the decoder are both energized to determine if a first predetermined signal condition has been received. The detection of this first signal condition activates the decoder and disrupts the battery saving power cycling to provide constant power to the receiver and the entire decoder so that selective calling signals can be received and decoded. Otherwise, the ON and OFF power cycling continues indefinitely.
In battery saver radios of this type, there has always been a problem associated with the interface between the discriminator or last stage of the receiver portion, which normally provides the recovered audio signal output, and the input of the signal processing circuitry of the decoder. The problem is that any coupling or interface circuit between the discriminator and the input of the processing circuit must satisfy several sometimes conflicting requirements, in that it must pass relatively low frequency selective calling signals to the processing circuitry; must be capable of responding quickly to signals that are received during the brief ON interval of the battery saver cycle; and must operate properly over a wide range of D.C. and A.C. output signal conditions that can exist at the output of the receiver due to the effects of temperature variations, supply voltage variations, frequency and amplitude shifts in the received signal, and tolerances associated with manufacturing.
The prior art selective signaling receivers respond to either tone or binary coding schemes, and commonly use an audio signal limiter as the first element of the signal processing circuitry of the decoder. This limiter amplifies and "clips" or "limits" the signals that appear at the output of the last stage of the receiver. That is, the limiter generates an output signal that has two amplitude levels which correspond to whether the instantaneous value of its input signal is above or below the average value of the signal. A signal limiter is used because it generates an output signal that has amplitude characteristics that are independent of several problems associated with the receiver including the amplitude and frequency of the input signal at the input of the receiver, manufacturing tolerances of components in the receiver, etc. Such a limiter also functions to eliminate amplitude variations in the recovered signals supplied to it thereby eliminating interferring amplitude modulation noise.
In the past, such a limiter has been capacitively coupled to the output of the receiver. The capacitance operates to help resolve the output bias variation problems that direct coupling could not overcome but a transient problem exists in that the time required to charge such a coupling capacitor has impacted the ability to return the limiter to a stable condition quickly enough after a power off period appropriate for the desired power savings. That is, the time required for the switching transients to die out sufficiently to allow for proper operation of the limiter can be quite long relative to the desired 100 millisecond ON period of a typical battery saver cycle. In a paging application, the bias on the limiter must be stabilized to within a few millivolts of its steady-state operating conditions in order to generate the correct zero crossings in the waveform that appears at the output of the limiter. As a result, a time interval equal to several time constants of the interstage coupling network must elapse after the circuitry is switched on before the limiter can be fully operational.
Since the receiver must be capable of receiving and decoding signals during the 100 millisecond ON period, the transient problem associated with the capacitive coupling would, if not corrected, require that the receiver be turned ON well before signal decoding is to begin, resulting in a longer effective ON time and a correspondingly reduced battery life.
This problem is particularly acute in pagers that use FSK binary signaling in that the coupling capacitor must be large enough to pass bit patterns that contain long strings of consecutive 1's or 0's without a DC level shift. This requirement means that the coupling network between the last stage of the receiver and the limiter must have a very long RC time constant which would be on the order of seconds. Such a long time constant would be diametrically opposed to the requirement for quickly establishing a stable operating condition when the receiver is switched on after a power off period of the battery saver circuit.
FIG. 1 describes in functional block diagram form the operation of a prior art receiver. An antenna 20 is coupled to a receiver 22. A B-plus voltage supply is coupled to receiver 22 through a switch 24. The output of receiver 22 is coupled through a switch 26 to a coupling capacitor 28, and ultimately to an input terminal of a data limiter 30. Battery saver circuit 32 is shown by a broken line as controlling the operation of switches 24 and 26. The output of the data limiter 30 is coupled to a signal processor 34. Switch 24 is also coupled to data limiter 30 and signal processor 34.
FIG. 1 shows one of several approaches that were developed in an attempt to solve the transient switching problem for battery saver receivers. Switch 26 is preferably a transistor switch connected in series with coupling capacitor 28 to isolate capacitor 28 when receiver 22 is in the off state as directed by battery saver circuit 32. That is switch 26 is open when the battery saver circuit switches receiver 22 off to avoid discharging capacitor 28 during the off mode of the duty cycle. Then when receiver 22 is switched on, switch 26 is closed to reconnect the limiter but the bias voltage on the capacitor 28 should be at substantially the magnitude required for proper operation. However, the circuit as exemplified in FIG. 1 does not work very well especially for very long battery saver off periods such as a 20 second interval. This is a result of the fact that leakage in the capacitor can cause a substantial discharge during the long OFF time period and thus cause a switching transient when the limiter is reconnected.
FIG. 2 is a functional block diagram of a second prior art approach to resolve the cycling problem of battery saver receivers. FIG. 2 shows an antenna 20 coupled to receiver 22 as before. A source of positive B-plus voltage is coupled through a switch 24 to receiver 22. The output of receiver 22 is coupled through a coupling capacitor 28 to a data limiter circuit 30. A battery saver circuit 32 is shown by a broken line as controlling switch 24 and, a signal processor 34 is coupled to the output of limiter 30. Switch 24 is also coupled to data limiter 30 and signal processor 34. A source of B-plus voltage is coupled to the emitter of a PNP transistor 36 whose collector is coupled through a resistor 37 to capacitor 28 and an input terminal of limiter 30. A control output of battery saver 32 is also coupled to a precharge control circuit 38 which is in turn coupled to the base of transistor 36.
The function of transistor 36 in its present position is to rapidly charge coupling capacitor 28 to the required bias level and thus shorten the length of the transient period that follows the off to on battery saver transition. Thus when the battery saver is first switched on, switch 24 is closed under the control of battery saver circuit 32. Transistor 36 functions as a simple switch which is used to lower the RC time constant of the coupling network between receiver 22 and the limiter 30 to allow the proper bias voltage level to be rapidly established on capacitor 28. Thus in effect, the RC time constant is altered to the value needed for proper operation of limiter 30 when power is restored.
This technique has been used with reasonable success, but it suffers from the problem that for FSK binary signalling the received bit stream must have nearly a fifty percent duty cycle of 1's and 0's during the time that capacitor 28 is being rapidly charged, otherwise the resultant bias voltage established on capacitor 28 is not the appropriate level needed for the correct operation of limiter 30.